Heterostructured Triple Strained DG FET for Nanotechnology

The book discusses the development and performance analysis of double gate strained-heterostructured-on-insulator FET for various technology nodes. Initially a 22nm channel length based FET incorporating the tri-layered strained system technology for the channel region is incorporated. This institutes ultrathin layers coagulating probable quantum carrier confinement, but to meet the urge of the device is scaled down to 14nm channel and subsequently the concept of underlap technology is processed for reducing the SCEs that are expected for the strained HOI channel in the NanoFET. The underlap length is varied from 1nm to 8nm and are investigated for quasi-ballistic effect and the reduced SCEs. On further downscaling to10nm channel, DG NanoFET is established leading to enhancement of 40.3% in comparison to existing 10nm DG FET at nano dimensions. Triple-strained channel technology based DG NanoFET can be employed as elementary building block for applications with amplified enactments in VLSI Circuits for RF, Ultra-fast switching for fast processor chips of future technologies.