CMOS Design

Instead of using conventional counter design technologies, a decision logic circuit isneeded to generate predictable counting states. In order to attain high operating frequency a high-speed parallel counter is presented. In our work the counter operating frequency is varied by using a parallel counter architecture of transmission gate base flip flops. The operation speed is improved by reduction of the critical path delay and the low power consumption is due to a smaller number of interconnects. The counter can be used as a frequency divider circuits. Each flip flops divide the input clock frequency by two. For generation of different clock frequencies, different counter structures are designed. Reduction in number of transistors will reduce the number of interconnect. The use of transmission gate also reduces number of stray capacitances and interconnect length, which in turn reduces the interconnect delay and power dissipation. In this work the structure of counter composes of three simple CMOS logic modules.